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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12601-1E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100A Series
MB95107A/F108AS/F108AW/FV100A-101
DESCRIPTION
The MB95100A series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions.
FEATURE
* F2MC-8FX CPU core Instruction set optimized for controllers * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instruction * Bit manipulation instructions etc. * Clock * Main clock * Main PLL clock * Subclock (for dual clock product) * Sub PLL clock (for dual clock product) (Continued)
PACKAGES
64-pin plastic LQFP 64-pin plastic LQFP
(FPT-64P-M03)
(FPT-64P-M09)
MB95100A Series
(Continued) * Timer * 8/16-bit compound timer x 2 channels * 16-bit reload timer * 8/16-bit PPG x 2 channels * 16-bit PPG x 2 channels * Timebase timer * Watch prescaler (for dual clock product) * LIN-UART * Full duplex double buffer * Clock asynchronous or synchronous serial transfer capable * UART/SIO * Clock asynchronous or synchronous serial transfer capable * I2C* * Built-in wake-up function * External interrupt * Interrupt by edge detection (rising, falling, or both edges can be selected) * Can be used to recover from low-power consumption modes. * 10-bit A/D converter * 10-bit resolution * Low-power consumption (standby mode) * Stop mode * Sleep mode * Watch mode (for dual clock product) * Timebase timer mode * I/O port: Max 55 * General-purpose I/O ports (Nch open drain) : 6 ports * General-purpose I/O ports (CMOS) : 49 ports * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
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MB95100A Series
PRODUCT LINEUP
Part number MB95107A Parameter Type ROM capacity RAM capacity Reset output Option Selectable Single/Dual -system*2 Single-system MASK product 48 KB 2 KB No Dual-system Selectable Single/Dual -system*1 FLASH product 60 KB 3.75 KB EVA product MB95F108AS MB95F108AW MB95FV100A-101
CPU functions
Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time
: 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 0.1 s (at internal 10 MHz) : 0.9 s (at internal 10 MHz) : 6 ports : 49 ports
Ports (Max 55 ports) Timebase timer Watchdog timer Wild register
General-purpose I/O port (Nch open drain) General-purpose I/O port (CMOS)
Interrupt cycle : 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Reset generated cycle At main oscillation clock 10 MHz : Min 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms Capable of replacing 3 bytes of data Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function Data transfer capable in UART/SIO Full duplex double buffer, Variable data length (5/6/7/8-bit), built-in baud rate generator Transfer rate : 2400 bps to 125000 bps (at machine clock 10 MHz) NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock synchronous (SIO) or clock asynchronous (UART) data transfer capable Dedicated reload timer allowing a wide range of communication speeds to be set. Capable of data transfer synchronous or asynchronous to clock signal. LIN functions available as the LIN master or LIN slave. 8-bit or 10-bit resolution can be selected. Two clock modes and two counter operating modes can be selected. Square waveform output Count clock : 7 internal clocks and external clock can be selected. (Continued)
Peripheral functions
I2C bus
UART/SIO
LIN-UART A/D converter (12 channels) 16-bit reload timer
3
MB95100A Series
(Continued) Part number MB95107A Parameter Each channel of the timer can be used as "8-bit timer x 2 channels" or "16-bit timer x 1 channel". 8/16-bit compound timBuilt-in timer function, PWC function, PWM function, capture function and Square er (2 channels) waveform output Count clock : 7 internal clocks and external clock can be selected. Peripheral functions 16-bit PPG (2 channels) 8/16-bit PPG (2 channels) PWM mode or one-shot mode can be selected. Counter operating clock : Eight selectable clock sources Support for external trigger start Each channel of the PPG can be used as "8-bit PPG x 2 channels" or "16-bit PPG x 1 channel". Counter operating clock : Eight selectable clock sources MB95F108AS MB95F108AW MB95FV100A-101
Watch counter Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) (for dual clock product) Counter value can be set from 0 to 63. (Capable of counting for 1 minute) Watch prescaler Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) (for dual clock product) External interrupt (12 channels) Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes. Sleep, stop, watch, and timebase timer
Standby mode
*1 : Change by the switch on MCU board. *2 : Specify clock mode when ordering MASK ROM.
4
MB95100A Series
SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK PRODUCT ONLY)
For the MASK product, you can set the mask option when ordering MASK ROM to select the initial value of main clock oscillation stabilization wait time from among the following four values. Note that the EVA and FLASH products are fixed their initial value of main clock oscillation stabilization wait time at the maximum value. Oscillation stabilization wait time (2 -2) /FCH (212-2) /FCH (213-2) /FCH (2 -2) /FCH
14 2
Remarks 0.5 s (at main oscillation clock 4 MHz) Approx. 1.02 ms (at main oscillation clock 4 MHz) Approx. 2.05 ms (at main oscillation clock 4 MHz) Approx. 4.10 ms (at main oscillation clock 4 MHz)
PACKAGES AND CORRESPONDING PRODUCTS
Part number Package FPT-64P-M03 FPT-64P-M09 BGA-224P-M08 : Available : Unavailable MB95107A MB95F108AS MB95F108AW MB95FV100A-101
5
MB95100A Series
DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
* Notes on Using EVA Products The EVA product has not only the functions of the MB95100A corresponding products series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/ O addresses for peripheral resources not used by the MB95100A series are therefore access-barred. Read/ write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Take particular care not to use word, long word, or similar access to read or write odd numbered bytes in the prohibited areas. Note that the values read from barred addresses are different between the EVA product and the FLASH or MASK product. Therefore, the data must not be used for software processing. The EVA product do not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. Since the EVA, FLASH, and MASK products are designed to behave completely the same way in terms of hardware and software, you do not have to pay special attention to specific products. * Difference of Memory Spaces If the amount of memory on the EVA product is different from that of the FLASH or MASK product, carefully check the difference in the amount of memory from the model to be actually used when developing software. * Current Consumption * The current consumption of FLASH product is typically greater than for MASK ROM product. * For details of current consumption, refer to " ELECTRICAL CHARACTERISTICS". * Package For details of information on each package, see " PACKAGE DIMENSIONS". * Operating voltage The operating voltage are different among the EVA, FLASH and MASK products. For details of operating voltage, refer to " ELECTRICAL CHARACTERISTICS" * Difference between RST and MOD pins The RST and MOD pins are hysteresis inputs on the MASK product. A pull - down resistor is provided for the MOD pin of the MASK product.
6
MB95100A Series
PIN ASSIGNMENT
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc AVR PE3/INT13 PE2/INT12 PE1/INT11 PE0/INT10 P83 P82 P81 P80 P71/TI0 P70/TO0 MOD X0 X1 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AVss P30/AN00 P31/AN01 P32/AN02 P33/AN03 P34/AN04 P35/AN05 P36/AN06 P37/AN07 P40/AN08 P41/AN09 P42/AN10 P43/AN11 P67/SIN P66/SOT P65/SCK
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P53/TRG1 P52/PPG1 P51/SDA0 P50/SCL0 P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P14/PPG0 P13/TRG0/ADTG
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Vcc PG0 PG2/X1A PG1/X0A RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12UCK0
7
MB95100A Series
PIN DESCRIPTION
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin name AVcc AVR PE3/INT13 PE2/INT12 PE1/INT11 PE0/INT10 P83 P82 P81 P80 P71/TI0 H P70/TO0 MOD X0 X1 Vss Vcc PG0 PG2/X1A PG1/X0A RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 G General-purpose I/O port. The pin is shared with UART/SIO ch0 data input. (Continued) C General-purpose I/O port. The pins are shared with external interrupt input. Large current port. B A H H/A B' General-purpose I/O port. The pin is shared with 16 - bit reload timer ch0 output. General-purpose I/O port. The pin is shared with 16 - bit reload timer ch0 input. An operating mode designation pin Crystal oscillation pin Power supply pin (GND) Power supply pin General-purpose I/O port. Single-system product is general-purpose port. Dual-system product is Crystal oscillation pin (32 kHz). Reset pin O General-purpose I/O port P General-purpose I/O port The pins are shared with the external interrupt input. Circuit type A/D power supply pin A/D reference input pin Description
8
MB95100A Series
Pin no. 31 32
Pin name P11/UO0 P12/UCK0 P13/TRG0/ ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P50/SCL0
Circuit type
Description General-purpose I/O port. The pin is shared with UART/SIO ch0 data output. General-purpose I/O port. The pin is shared with UART/SIO ch0 clock I/O.
H
33
General-purpose I/O port. The pin is shared with 16-bit PPG ch0 trigger input (TRG0) and A/D trigger input (ADTG). General-purpose I/O port. The pin is shared with 16-bit PPG ch0 output. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch0 output.
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
H
General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch0 output. General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch0 clock input. General-purpose I/O port. The pin is shared with I2C ch0 clock I/O. General-purpose I/O port. The pin is shared with I2C ch0 data I/O. General-purpose I/O port. The pin is shared with 16-bit PPG ch1 output. General-purpose I/O port. The pin is shared with 16-bit PPG ch1 trigger input. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch1 output. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch1 output.
I P51/SDA0 P52/PPG1 H P53/TRG1 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 P65/SCK P66/SOT P67/SIN P43/AN11 P42/AN10 P41/AN09 P40/AN08 J L K
General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch1 clock input. General-purpose I/O port. The pin is shared with LIN-UART clock I/O. General-purpose I/O port. The pin is shared with LIN-UART data output. General-purpose I/O port. The pin is shared with LIN-UART data input.
General-purpose I/O port. The pins are shared with A/D analog input.
(Continued) 9
MB95100A Series
(Continued) Pin no. 56 57 58 59 60 61 62 63 64 Pin name P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVss A/D power supply pin (GND) J General-purpose I/O port. The pins are shared with A/D analog input. Circuit type Description
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MB95100A Series
I/O CIRCUIT TYPE
Type Circuit Remarks * Oscillation circuit * High-speed side Feedback resistance value : approx. 1 M * Low-speed side Feedback resistance : approx. 24 M (EVA product : approx. 10 M) Dumping resistance : approx. 144 k (EVA product : without dumping resistance) * Only for input Hysteresis input only for MASK product With pull-down resistor only for MASK product * Hysteresis input only for MASK product B' * CMOS output * Hysteresis input
X1 (X1A)
A
X0 (X0A)
Standby control
B
R
Pch
C Standby control
External interrupt enable
Nch
R Pch
Pull-up control
* * * *
CMOS output CMOS input Hysteresis input With pull - up control
G
Nch
Standby control * CMOS output * Hysteresis input * With pull - up control
R Pch
Pull-up control
H
Nch
Standby control (Continued)
11
MB95100A Series
(Continued) Type
Circuit
Remarks * Nch open drain output * CMOS input * Hysteresis input
Nch
I Standby control
R Pch
Pull-up control
* * * *
CMOS output Hysteresis input Analog input With pull - up control
J
Nch
Analog input A/D control Standby control
Pch
* CMOS output * Hysteresis input
K
Nch
Standby control
Pch
* CMOS output * CMOS input * Hysteresis input
L
Nch
Standby control * Nch open drain output * Hysteresis input O Standby control * CMOS output * Hysteresis input * With pull - up control
Nch
R Pch
Pull-up control
P
Nch
Standby control External interrupt control
12
MB95100A Series
HANDLING DEVICES
* Preventing Latchup Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC, AVR) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. * Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power-supply voltage. For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range (50 Hz to 60 Hz) not to exceed 10% of the Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. * Treatment of Unused Input Pin An unused input pin may cause a malfunction if it is left open. It should be connected to a pull-up or pull-down resistor. * Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use. * Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. * Precaution against Noise to the External Reset Pin (RST) An input of a reset pulse below the specified level to the external reset pin (RST) may cause malfunctions. Be sure not to allow an input of a reset pulse below the specified level to the external reset pin (RST).
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MB95100A Series
PROGRAMMING FLASH MICROCONTROLLERS USING PARALLEL PROGRAMMER
* Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-64P-M03 FPT-64P-M09 TEF110-108F35AP TEF110-108F36AP Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more)
Notes: * Set all of the J1 to J3 switches on the adapter to "95F108". * For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: 053-428-8380 * Sector Configuration The individual sectors of flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: FLASH memory SA1 (4 Kbytes) SA2 (4Kbytes) 2FFFH 3000H SA3 (4 Kbytes) 3FFFH 4000H SA4 (16 Kbytes) 7FFFH 8000H SA5 (16 Kbytes) BFFFH C000H SA6 (4 Kbytes) CFFFH D000H SA7 (4 Kbytes) DFFFH E000H SA8 (4 Kbytes) EFFFH F000H SA9 (4 Kbytes) FFFFH 7FFFFH *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into flash memory. These programmer addresses are used for the parallel programmer to program or erase data in flash memory. * Programming Method 1) Set the type code of the parallel programmer to 17226. 2) Load program data to programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer 14 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H 7BFFFH 7C000H
Upper bank Lower bank
CPU address 1000H 1FFFH 2000H
Writer address* 71000H 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H
MB95100A Series
BLOCK DIAGRAM
F MC-8FX CPU RST X0,X1 PG2/X1A* PG1/X0A* PG0 Reset control Clock control Watch prescaler Watch counter P00/INT00 ~ P07/INT07 P10/UI0 P11/UO0 P12/UCK0 16 bit-PPG ch0 Internal bus P13/TRG0/ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0 P30/AN00 ~ P37/AN07 P40/AN08 ~ P43/AN11 AVCC AVSS AVR P50/SCL0 P51/SDA0 P52/PPG1 P53/TRG1 I 2C 10-bit A/D converter
External interrupt ch8 to ch11 External interrupt ch0 to ch7
2
ROM RAM Interrupt control Wild register
8/16-bit PPG ch1
P60/PPG10 P61/PPG11 P62/TO10
UART/SIO 8/16-bit compound timer ch1
P63/TO11 P64/EC1 P65/SCK
LIN-UART
8/16-bit PPG ch0
P66/SOT P67/SIN P70/TO0 P71/TI0 P80 ~ P83 PE0/INT10 ~ PE3/INT13
8/16-bit compound timer ch0
16-bit reload timer
16-bit PPG ch1 Port Port
Other pins
MOD, VCC, VSS
* : Single-system product is general-purpose port, and dual-system product is subclock oscillation.
15
MB95100A Series
CPU CORE
1. Memory space
Memory space of the MB95100A series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special - purpose areas such as the general - purpose registers and vector table. Memory map of the MB95100A series is shown in below.
* Memory Map
MB95107A 0000H I/O 0080H 0100H 0200H 0880H 0F80H I/O 1000H Access prohibited 4000H FLASH 60 KB FLASH 60 KB 1000H RAM 2 KB
Register
MB95F108A 0000H I/O 0080H RAM 2 KB 0100H Register 0200H 0880H 0F80H I/O 0000H
MB95FV100A-101 I/O 0080H RAM 3.75 KB 0100H Register 0200H
Access prohibited
Access prohibited 0F80H I/O 1000H
ROM 48 KB FFFFH FFFFH FFFFH
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MB95100A Series
2. Register
The MB95100A series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register
16-bit
PC A T IX EP SP PS
Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR) . (See the diagram below.) * Structure of the program status
15 PS R4 14 R3 13 R2 12 R1 11 R0 10 DP2 9 DP1 8 DP0 7 H 6 I 5 IL1 4 IL0 3 N 2 Z 1 V 0 C
RP
DP
CCR
17
MB95100A Series
The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: * Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper
"0" "0" "0" "0" "0" "0" "0" "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3
OP code lower
b2 A2 b1 A1 b0 A0
Generated address A15 A14 A13 A12 A11 A10 A9
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area Don't care 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. : Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to "1". Interrupt is disabled when this flag is set to "0". The flag is set to "0" when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low = no interruption Priority High H flag
: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Cleared to "0" when the
bit is set to "0".
: Set to "1" when an arithmetic operation results in 0. Cleared to "0" otherwise. : Set to "1" if the complement on 2 overflows as a result of an arithmetic operation. Cleared to "0"
otherwise. : Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. Set to the shift-out vallue in the case of a shift instruction.
18
MB95100A Series
The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB95100A series. The bank currently in use is indicated by the register bank pointer (RP). * Register Bank Configuration This address = 0100H + 8 x (RP)
R0 R1 R2 R3 R4 R5 R6 R7
32 banks
Memory area
19
MB95100A Series
I/O MAP
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH to 0025H 0026H 0027H 0028H 0029H 002AH 20 Register abbreviation PDR0 DDR0 PDR1 DDR1 WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC PDR2 DDR2 PDR3 DDR3 PDR4 DDR4 PDR5 DDR5 PDR6 DDR6 PDR7 DDR7 PDR8 DDR8 PDRE DDRE PDRG Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Vacancy) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register (Vacancy) Port 2 data register Port 2 direction register Port 3 data register Port 3 direction register Port 4 data register Port 4 direction register Port 5 data register Port 5 direction register Port 6 data register Port 6 direction register Port 7 data register Port 7 direction register Port 8 data register Port 8 direction register (Vacancy) Port E data register Port E direction register (Vacancy) Port G data register R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 0000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
MB95100A Series
Address 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H 0049H 004AH 004BH 004CH 004DH
Register abbreviation DDRG PUL1 PUL2 PUL3 PUL4 PUL5 PUL7 PULE PULG T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 TMCSRH0 TMCSRL0 PCNTH0 PCNTL0 PCNTH1 PCNTL1 EIC00 EIC10 EIC20 EIC30 EIC01 EIC11
Register name Port G direction register (Vacancy) Port 1 pull - up register Port 2 pull - up register Port 3 pull - up register Port 4 pull - up register Port 5 pull - up register Port 7 pull - up register (Vacancy) Port E pull - up register Port G pull - up register 8/16-bit compound timer 01 control status register 1 ch0 8/16-bit compound timer 00 control status register 1 ch0 8/16-bit compound timer 11 control status register 1 ch1 8/16-bit compound timer 10 control status register 1 ch1 8/16-bit PPG1 control register ch0 8/16-bit PPG0 control register ch0 8/16-bit PPG1 control register ch1 8/16-bit PPG0 control register ch1 16-bit reload timer control status register (Upper byte) ch0 16-bit reload timer control status register (Lower byte) ch0 (Vacancy) 16-bit PPG control status register (Upper byte) ch0 16-bit PPG control status register (Lower byte) ch0 16-bit PPG control status register (Upper byte) ch1 16-bit PPG control status register (Lower byte) ch1 (Vacancy) External interrupt circuit control register ch0/1 External interrupt circuit control register ch2/3 External interrupt circuit control register ch4/5 External interrupt circuit control register ch6/7 External interrupt circuit control register ch8/9 External interrupt circuit control register ch10/11
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 21
MB95100A Series
Address 004EH 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H
Register abbreviation SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 ADC1 ADC2 ADDH ADDL WCSR FSR SWRE0 SWRE1 WREN WROR
Register name (Vacancy) LIN-UART serial control register LIN-UART serial mode register LIN-UARTserial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch0 UART/SIO serial mode control register 2 ch0 UART/SIO serial status register ch0 UART/SIO serial output data register ch0 UART/SIO serial input data register ch0 (Vacancy) I2C bus control register 0 ch0 I2C bus control register 1 ch0 I C bus status register ch0 I C data register ch0 I2C address register ch0 I2C clock control register ch0 (Vacancy) A/D control register 1 A/D control register 2 A/D data register (Upper byte) A/D data register (Lower byte) Watch counter status register (Vacancy) FLASH memory status register FLASH memory sector writing control register 0 FLASH memory sector writing control register 1 (Vacancy) Wild register address compare enable register Wild register data test setting register
2 2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 000X0000B 00000000B 00000000B 00000000B 00000000B (Continued)
22
MB95100A Series
Address 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH
Register abbreviation ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00
Register name (Mirror of register bank pointer (RP) and direct bank pointer (DP) ) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Vacancy) Wild register address setting register (Upper byte) ch0 Wild register address setting register (Lower byte) ch0 Wild register data setting register ch0 Wild register address setting register (Upper byte) ch1 Wild register address setting register (Lower byte) ch1 Wild register data setting register ch1 Wild register address setting register (Upper byte) ch2 Wild register address setting register (Lower byte) ch2 Wild register data setting register ch2 (Vacancy) 8/16-bit compound timer 01 control status register 0 ch0 8/16-bit compound timer 00 control status register 0 ch0 8/16-bit compound timer 01 data register ch0 8/16-bit compound timer 00 data register ch0 8/16-bit compound timer 00/01 timer mode control register ch0 8/16-bit compound timer 11 control status register 0 ch1 8/16-bit compound timer 10 control status register 0 ch1 8/16-bit compound timer 11 data register ch1 8/16-bit compound timer 10 data register ch1 8/16-bit compound timer 10/11 timer mode control register ch1 8/16-bit PPG1 cycle setting buffer register ch0 8/16-bit PPG0 cycle setting buffer register ch0 8/16-bit PPG1 duty setting buffer register ch0 8/16-bit PPG0 duty setting buffer register ch0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B (Continued) 23
MB95100A Series
Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H 0FC1H 0FC2H 0FC3H 0FC4H to 0FE2H
Register abbreviation PPS11 PPS10 PDS11 PDS10 PPGS REVC TMRH0/ TMRLRH0 TMRL0/ TMRLRL0 PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 PDCRH1 PDCRL1 PCSRH1 PCSRL1 PDUTH1 PDUTL1 BGR1 BGR0 PSSR0 BRSR0 AIDRH AIDRL
Register name 8/16-bit PPG1 cycle setting buffer register ch1 8/16-bit PPG0 cycle setting buffer register ch1 8/16-bit PPG1 duty setting buffer register ch1 8/16-bit PPG0 duty setting buffer register ch1 8/16-bit PPG start register 8/16-bit PPG output inversion register 16-bit timer register (Upper byte) ch0/ 16-bit reload register (Upper byte) ch0 16-bit timer register (Lower byte) ch0/ 16-bit reload register (Lower byte) ch0 (Vacancy) 16-bit PPG down counter register (Upper byte) ch0 16-bit PPG down counter register (Lower byte) ch0 16-bit PPG cycle setting buffer register (Upper byte) ch0 16-bit PPG cycle setting buffer register (Lower byte) ch0 16-bit PPG duty setting buffer register (Upper byte) ch0 16-bit PPG duty setting buffer register (Lower byte) ch0 16-bit PPG down counter register (Upper byte) ch1 16-bit PPG down counter register (Lower byte) ch1 16-bit PPG cycle setting buffer register (Upper byte) ch1 16-bit PPG cycle setting buffer register (Lower byte) ch1 16-bit PPG duty setting buffer registe (Upper byte) ch1 16-bit PPG duty setting buffer register (Lower byte) ch1 (Vacancy) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO prescaler selection register ch0 UART/SIO baud rate setting register ch0 (Vacancy) A/D input disable register (Upper byte) A/D input disable register (Lower byte) (Vacancy)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
24
MB95100A Series
(Continued) Address 0FE3H 0FE4H to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation WCDR ILSR WICR Register name Watch counter data register (Vacancy) Input level select register Interrupt pin control register (Vacancy) R/W R/W R/W R/W Initial value 00111111B 00000000B 01000000B
* Read/write access symbols R/W : Readable and Writable R : Read only W : Write only * Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined.
25
MB95100A Series
INTERRUPT SOURCE TABLE
Interrupt source External interrupt ch0 External interrupt ch4 External interrupt ch1 External interrupt ch5 External interrupt ch2 External interrupt ch6 External interrupt ch3 External interrupt ch7 UART/SIO ch0 8/16-bit compound timer ch0 (Lower) 8/16-bit compound timer ch0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch1 (Lower) 8/16-bit PPG ch1 (Upper) 16-bit reload timer ch0 8/16-bit PPG ch0 (Upper) 8/16-bit PPG ch0 (Lower) 8/16-bit compound timer ch1 (Upper) 16-bit PPG ch0 I2C ch0 16-bit PPG ch1 10-bit A/D converter Timebase timer Watch timer/counter External interrupt ch8 External interrupt ch9 External interrupt ch10 External interrupt ch11 8/16-bit compound timer ch1 (Lower) FLASH IRQ22 IRQ23 FFCEH FFCCH FFCFH FFCDH L22 [1 : 0] L23 [1 : 0] Low IRQ21 FFD0H FFD1H L21 [1 : 0] Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] High
26
MB95100A Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol Vcc AVcc AVR Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current "L" level maximum output current VI1 VI2 VO ICLAMP |ICLAMP| IOL1 IOL2 Rating Min Vss - 0.3 Vss - 0.3 Vss - 0.3 Vss - 0.3 Vss - 0.3 - 2.0 Max Vss + 4.0 Vss + 4.0 Vss + 4.0 Vss + 6.0 Vss + 4.0 + 2.0 20 15 15 V V mA mA mA Unit *2 *2 Other than P50, P51, P80 to P83*3 P50, P51, P80 to P83 *3 Applicable to pins*4 Applicable to pins*4 Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin) Remarks
Power supply voltage*
1
V
IOLAV1 "L" level average current IOLAV2
4 mA 12
"L" level total maximum output current "L" level total average output current "H" level maximum output current
IOL IOLAV IOH1 IOH2

100
mA Total average output current = operating current x operating ratio (Total of pins) Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin)
50 - 15 - 15 -4
mA
mA
IOHAV1 "H" level average current IOHAV2
mA -8
"H" level total maximum output current "H" level total average output current
IOH IOHAV

- 100 - 50
mA Total average output current = operating current x operating ratio (Total of pins) (Continued) 27
mA
MB95100A Series
(Continued) Parameter Power consumption Operating temperature Storage temperature Symbol Pd TA Tstg Rating Min - 40 - 55 Max 320 + 85 + 150 Unit mW C C Other than MB95FV100A-101 Remarks
*1 : The parameter is based on AVSS = VSS = 0.0 V. *2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V. *3 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI1 rating. *4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71, PE0 to PE3, PG0 * Use within recommended operating conditions. * Use at DC voltage (current). * The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. * The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. * Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the + B input pin open. * Sample recommended circuits : * Input/Output Equivalent circuits Protective diode Limiting resistance
Vcc Pch Nch R
+ B input (0 V to 16 V)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
MB95100A Series
2. Recommended Operating Conditions
(AVss = Vss = 0.0 V) Parameter Symbol Value Min 1.8*1 1.8*1 2.0*1 Power supply voltage VCC, AVCC 2.0*1 2.6 1.5 1.5 A/D converter reference input voltage Operating temperature AVR TA 1.8 - 40 Max 3.3*2 3.6 3.3*2 3.6
V
Unit
Remarks At normal operating, FLASH product, TA = -10 C to +85 C At normal operating, MASK product, TA = -10 C to +85 C At normal operating, FLASH product, TA = -40 C to +85 C At normal operating, MASK product, TA = -40 C to +85 C MB95FV100A-101 Retain status of stop operation, FLASH product Retain status of stop operation, MASK product
3.6 3.3*2 3.6 AVCC + 85 C
Other than MB95FV100A-101
*1 : The values vary with the operating frequency. *2 : Consult Fujitsu separately for a guarantee of a maximum value of 3.6 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
29
MB95100A Series
3. DC Characteristics
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C [MB95FV100A-101 is TA = + 25 C]) Parameter
Symbol
Pin name
Conditions *1
Value Min 0.7 Vcc Typ Max Vcc + 0.3
Unit
Remarks At selecting of CMOS input level (hysteresis input) At selecting of CMOS input level (hysteresis input)
VIH1 P10, P67
V
VIH2 P50, P51 P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, VIHS1 P52, P53, P60 to P67, P70, P71, PE0 to PE3, PG0, PG1*2, PG2*2 VIHS2 P50, P51, P80 to P83
*1
0.7 Vcc
Vss + 5.5
V
"H" level input voltage
*1
0.8 Vcc
Vcc + 0.3
V
Hysteresis input
*1
0.8 Vcc 0.7 Vcc 0.8 Vcc Vss - 0.3

Vss + 5.5 Vcc + 0.3 Vcc + 0.3 0.3 Vcc
V V V
Hysteresis input CMOS input (FLASH product) Hysteresis input (MASK product) At selecting of CMOS input level (hysteresis input)
VIHM RST, MOD VIL P10, P50, P51, P67 *1
V
"L" level input voltage
P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, VILS P50 to P53, P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG0, PG1*2, PG2*2
*1
Vss - 0.3
0.2 Vcc
V
Hysteresis input
VILM RST, MOD Open-drain output application voltage
Vss - 0.3 Vss - 0.3

0.3 Vcc 0.2 Vcc
V V
CMOS input (FLASH product) Hysteresis input (MASK product)
VD
P50, P51, P80 to P83
Vss - 0.3
Vss + 5.5
V
VOH1 "H" level output voltage
Output pin other than IOH = P00 to P07 - 4.0 mA IOH = - 8.0 mA
2.4
V
MB95FV100A-101 a conditional : IOH = - 2.0 mA MB95FV100A-101 a conditional : IOH = - 5.0 mA (Continued)
VOH2 P00 to P07
2.4
V
30
MB95100A Series
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C [MB95FV100A-101 is TA = + 25 C]) Parameter Sym bol VOL1 "L" level output voltage Pin name Output pin other than P00 to P07 Conditions Value Min Typ Max 0.4 Unit Remarks MB95FV100A-101 a conditional : IOL = 3.0 mA MB95FV100A-101 a conditional : IOL = 8.0 mA
IOL = 4.0 mA
V
VOL2 P00 to P07 Input leakage current (High-Z output leakage current) Open-drain output leakage current
IOL = 12 mA
0.4
V
ILI
Port other than P50, P51, P80 to P83 P50, P51, P80 to P83
0.0 V < VI < Vcc
-5
+5
When no pull-up A resistor is specified A
ILIOD
0.0 V < VI < Vss + 5.5 V
+5
P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, Pull-up resistor RPULL VI = 0.0 V P53, P70, P71, PE0 to PE3, PG0, PG1*2, PG2*2 Pull-down resistor RMOD MOD VI = Vcc FCH = 20 MHz fmp = 10 MHz Main clock mode (divided by 2) FCH = 20 MHz fmp = 10 MHz Main Sleep mode Vcc (External clock (divided by 2) operation) FCL = 32 kHz fmpl = 16 kHz Subclock mode (divided by 2) , TA = + 25 C FCL = 32 kHz fmpl = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 C
25
50
100
k
When specifying pull-up resistor
50
100 11 7.3 30
200 14 10 35
k
MASK product only
mA FLASH product mA MASK product FLASH product (at mA FLASH writing and erasing)
ICC
ICCS Power supply current*3 ICCL
4.5
6
mA
25
35
A
ICCLS
7
15
A
(Continued)
31
MB95100A Series
(Continued) (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C [MB95FV100A-101 is TA = + 25 C]) Parameter Symbol Pin name Conditions FCL = 32 kHz Watch mode Main stop mode TA = + 25 C FCH = 4 MHz fmp = 10 MHz Main PLL mode (multiplied by 2.5) FCL = 32 kHz fmpl = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 C FCH = 10 MHz Timebase timer mode TA = + 25 C Sub stop mode TA = + 25 C FCH = 10 MHz At operating of A/D conversion AVcc IAH FCH = 10 MHz At stopping A/D conversion TA = + 25 C Value Min Typ 2 1 10 6.7 Max 10 5 14 10 Unit Remarks
A FLASH product A MASK product mA FLASH product mA MASK product
ICCT
ICCMPLL VCC (External clock ICCSPLL operation) Power supply current*3 ICTS
190
250
A
0.4
0.5
mA
ICCH

1
5
A mA
IA
1.3
2.2
1
5
A
Input capacitance
CIN
Other than AVcc, AVss, AVR, Vcc, Vss
5
15
pF
*1 : P10, P50, P51, and P67 can switch the input level to either the CMOS input level or hysteresis input level. The switching of the input level can be set by the input level selection register (ILSR). *2 : Single-clock product only *3 : The power-supply current is determined by the external clock. * Refer to "4. AC characteristics (1) Clock Timing" for FCH and FCL. * Refer to "4. AC characteristics (2) Source Clock/Machine Clock" for fmp and fmpl.
32
MB95100A Series
4. AC Characteristics
(1) Clock Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin Conditions Value Min 1 1 FCH X0, X1 3 3 Clock frequency 3 FCL X0A, X1A 100 50 tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0A, X1A X0 X0A X0, X0A 10 30.5 15.2 1000 1000 5 ns ns s ns s ns 32.768 kHz Typ 32.768 Max 10 20 10 5 4 Unit MHz Remarks When using Main oscillation circuit
MHz When using external clock MHz Main PLL multiplied by 1 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 kHz When using Sub oscillation circuit When using sub PLL FLASH product : Vcc = 2.3 V to 3.3 V MASK product : Vcc = 2.3 V to 3.6 V When using Main oscillation circuit When using external clock When using Sub oscillation circuit When using external clock Duty ratio is about 30% to 70%. When using external clock
tHCYL Clock cycle time
X0, X1
Input clock pulse width
Input clock rise time and fall time
33
MB95100A Series
* X0 and X1 Timing and Applying Conditions
tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1
X0
* Main Clock Applying Conditions When using a crystal or ceramic oscillator
When using external clock
X0
X1 FCH
X0
X1
Open
FCH
* X0A and X1A Timing and Applying Conditions
tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC 0.1 VCC tWL2
X0A
* SubClock Applying Conditions When using a crystal or ceramic oscillator
When using external clock
X0A
X1A FCL
X0A
X1A
Open
FCL
34
MB95100A Series
(2) Source Clock/Machine Clock (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter SymPin bol name Value Min Typ Max Unit Remarks When using Main clock Min : FCH = 10 MHz, PLL multiplied by 1 Max : FCH = 1 MHz, divided by 2 When using Subclock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2
100 Source clock* (Clock before setting division)
1
2000
ns
SCLK
7.6 61.0 s
Source clock frequency
fsp fspl
0.5 16.384
10.0
MHz When using Main clock When using Main clock Min : SLCK = 10 MHz, no division Max : SLCK = 0.5 MHz, divided by 16 When using Subclock Min : SLCK = 131 kHz, no division Max : SLCK = 16 kHz, divided by 16
131.072 kHz When using Subclock
100 Machine clock* (Minimum instruction execution time)
2
32000
ns
MCLK
7.6 976.5 s
Machine clock frequency
fmp fmpl
0.031 1.024
10.000
MHz When using Main clock
131.072 kHz When using Subclock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follow. * Main clock divided by 2 * PLL multiplication of main clock (select from 1, 2, 2.5 multiplication) * Subclock divided by 2 * PLL multiplication of subclock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follow. * Source clock (no division) * Source clock divided by 4 * Source clock divided by 8 * Source clock divided by 16
35
MB95100A Series
* Operating voltage - Operating frequency * MASK product Sub PLL operation guarantee range (2.3 V to 3.6 V)
3.6
A/D converter accuracy guarantee range
Main PLL operation guarantee range Operating voltage (V)
2.2 2.0 1.8
1.0
0.5 MHz
3 MHz
5 MHz
10 MHz
Source clock frequency (fsp) * FLASH product Sub PLL operation guarantee range
(2.3 V to 3.3 V)
3.3
A/D converter accuracy guarantee range
Main PLL operation guarantee range Operating voltage (V)
2.2 2.0 1.8
1.0
0.5 MHz
3 MHz
5 MHz
10 MHz
Source clock frequency (fsp) Note: In operating by 2.0 V or less, only "TA = -10 C to +85 C" is guaranteed. (Continued) 36
MB95100A Series
(Continued) * Main PLL operation frequency
10 MHz
Source clock frequency (fsp)
9 MHz 8 MHz 7.5 MHz 7 MHz 6 MHz 5 MHz 4 MHz 3 MHz
x 2.5 x2 x1
3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz
Main clock frequency
37
MB95100A Series
(3) Reset Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter RST "L" level pulse width Symbol Value Min 2 MCLK*1 tRSTL Oscillation time of oscillator*2 + 2 MCLK*1 Max Unit ns ns Remarks At normal operating At stop mode, subclock mode, sub sleep mode, and watch mode
*1 : Refer to " (2) Source Clock/Machine Clock" for MCLK. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In FAR/ceramic oscillators, the oscillation time is between hundreds of s and several ms. In the external clock, the oscillation time is 0 ms. * At normal operating
tRSTL
RST
0.2 VCC 0.2 VCC
* At stop mode, subclock mode, sub sleep mode, and watch mode
tRSTL 0.2 VCC 0.2 VCC
RST
90% of amplitude
X0
Internal operating clock Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset
2 MCLK
38
MB95100A Series
(4) Power-on Reset (AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions Value Min 1 Max 36 Unit ms ms Due to repeated operations Remarks
Note : The power supply must be turned on within the selected oscillation stabilization time.
tR 1.5 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 20 mV/ms as shown below. In this case, do not use PLL clock. However, if voltage drop is 1V/s or less, use of PLL clock is allowed during operation.
VCC
1.5 V
Limiting the slope of rising within 20 mV/ms is recommended. RAM data hold period
VSS
39
MB95100A Series
(5) Peripheral Input Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol
tILIH tIHIL
Pin name INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1
Value Min 2 MCLK* 2 MCLK* Max
Unit ns ns
Remarks
* : Refer to " (2) Source Clock/Machine Clock" for MCLK.
tILIH
tIHIL
INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
40
MB95100A Series
(6) UART/SIO, Serial I/O Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time UCK UO time Valid UI UCK UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time Valid UI UCK UCK valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation Internal clock operation Conditions Value Min 4 MCLK* - 190 2 MCLK* 2 MCLK* 4 MCLK* 4 MCLK* 2 MCLK* 2 MCLK* Max 190 190 Unit ns ns ns ns ns ns ns ns ns Remarks
* : Refer to " (2) Source Clock/Machine Clock" for MCLK.
* Internal shift clock mode
tSCYC
UCK0
2.4 V 0.8 V tSLOV 0.8 V
UO0
2.4 V 0.8 V tIVSH tSHIX VIH VIL
UI0
VIH VIL
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV
UCK0
UO0
2.4 V 0.8 V tIVSH tSHIX VIH VIL
UI0
VIH VIL
41
MB95100A Series
(7) LIN-UART Timing ESCR : SCES = 0, ECCR : SCDE = 0 SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL SCK SCK, SOT SCK, SIN SCK, SIN SCK SCK External clock operation output pin : CL = 80 pF + 1 TTL Internal clock operation output pin : CL = 80 pF + 1 TTL (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Conditions Value Min 5 MCLK* -95 MCLK* + 190 0 3 MCLK* - tR MCLK* + 95 190 MCLK* + 95 Max 95 2 MCLK* + 95 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SINSCK SCK valid SIN hold time Serial clock "L" pulse width Serial clock "H" pulse width SCK SOT delay time Valid SINSCK SCK valid SIN hold time SCK fall time SCK rise time
tSLOVE SCK, SOT tIVSHE tSHIXE tF tR SCK, SIN SCK, SIN SCK SCK
* : Refer to " (2) Source Clock/Machine Clock" for MCLK.
42
MB95100A Series
* Internal shift clock mode
tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI
SCK
SOT
SIN
VIH VIL
* External shift clock mode
tSLSH tSHSL VIH VIL tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE tR
SCK
SOT
SIN
VIH VIL
43
MB95100A Series
ESCR : SCES = 1, ECCR : SCDE = 0 Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK SCK SCK, SOT SCK, SIN SCK, SIN SCK SCK External clock operation output pin : CL = 80 pF + 1 TTL Conditions Value Min 5 MCLK* Internal clock -95 operation output pin : CL = 80 pF + 1 TTL MCLK* + 190 0 3 MCLK* - tR MCLK* + 95 190 MCLK* + 95 Max 95 2 MCLK* + 95 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SINSCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SINSCK SCK valid SIN hold time SCK fall time SCK rise time
* : Refer to " (2) Source Clock/Machine Clock" for MCLK.
44
MB95100A Series
* Internal shift clock mode
tSCYC
SCK
2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI
SOT
SIN
VIH VIL
* External shift clock mode
tSHSL tSLSH
SCK
VIH VIL tR tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF
SOT
SIN
VIH VIL
45
MB95100A Series
ESCR : SCES = 0, ECCR : SCDE = 1 Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Conditions Value Min 5 MCLK* -95 Internal clock operation output pin : MCLK* + 190 CL = 80 pF + 1 TTL 0 Max 95 4 MCLK* Unit ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SINSCK SCK valid SIN hold time SOTSCK delay time
* : Refer to " (2) Source Clock/Machine Clock" for MCLK.
tSCYC
SCK
0.8 V tSOVLI 2.4 V 0.8 V tIVSLI tSLIXI
2.4 V
tSHOVI
2.4 V 0.8 V
0.8 V
SOT
SIN
VIH VIL
VIH VIL
46
MB95100A Series
ESCR : SCES = 1, ECCR : SCDE = 1 Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Pin name SCK SCK, SOT Conditions Value Min 5 MCLK* Max 95 4 MCLK* Unit ns ns ns ns ns
Parameter Serial clock cycle time SCKSOT hold time Valid SINSCK SCK valid SIN hold time SOTSCK delay time
-95 Internal clock SCK, SIN operating output pin : MCLK* + 190 CL = 80 pF + 1 TTL SCK, SIN 0
SCK, SOT
* : Refer to " (2) Source Clock/Machine Clock" for MCLK.
tSCYC
SCK
tSOVHI
2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI VIH VIL 2.4 V 0.8 V
2.4 V
SOT
SIN
VIH VIL
47
MB95100A Series
(8) I2C Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Value Parameter SCL clock frequency (Repeat) Start condition hold time SDA SCL SCL clock "L" width SCL clock "H" width (Repeat) Start condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL Stop condition setup time SCL SDA Bus free time between stop condition and start condition Symbol Conditions Standard-mode Min fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF R = 1.7 k, C = 50 pF*1 0 4.0 4.7 4.0 4.7 0 0.25 4 4.7 Max 100 3.45*2 Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 0.9*3 kHz s s s s s s s s Unit Remarks
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the "L" width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met.
tWAKEUP SDA0 tLOW SCL0 tHD;STA tHD;DAT tSU;STA tSU;STO tSU;DAT tHIGH tHD;STA tBUF
48
MB95100A Series
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Parameter SCL clock "L" width SCL clock "H" width Symbol tLOW tHIGH I/O Timing Min (2 + nm*2 / 2) MCLK*1 - 20 (nm*2 / 2) MCLK*1 - 20 (-1 + nm* / 2) MCLK*n1 - 20
2
Max (nm*2 / 2 ) MCLK*1 + 20 (-1 + nm* ) MCLK*1 + 20
2
Unit ns ns
Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode
Start condition hold time
tHD;STA
ns
Stop condition setup time Start condition setup time Bus free time between stop condition and start condition Data hold time
tSU;STO tSU;STA tBUF tHD;DAT
(1 + nm*2 / 2) MCLK*n1 - 20 (1 + nm*2 / 2) MCLK*1 - 20 (2 nm*2 + 4) MCLK*1 - 20 3 MCLK*1 - 20
(1 + nm*2 / 2) MCLK*1 + 20 (1 + nm*2 / 2) MCLK*1 + 20
ns ns ns ns
Master mode Master mode When assuming that "L" of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL. Maximum value is applied to interrupt at 8th SCL. At reception At reception Undetected when 1 MCLK is used at reception Undetected when 1 MCLK is used at reception Undetected when 1 MCLK is used at reception At reception At slave transmission mode At slave transmission mode At reception At reception (Continued) 49
Data setup time
tSU;DAT
(-2 + nm*2 / 2) MCLK*1 - 20
(-1 + nm*2 / 2) MCLK*1 + 20
ns
Setup time between clearing interrupt and SCL rising SCL clock "L" width SCL clock "H" width Start condition detection Stop condition detection Restart condition detection condition Bus free time Data hold time Data setup time Data hold time Data setup time
tSU;INT
(nm*2 / 2) MCLK*1 - 20 4 MCLK*1 - 20 4 MCLK*1 - 20 2 MCLK*1 - 20 2 MCLK*1 - 20 2 MCLK*1 - 20 2 MCLK*1 - 20 2 MCLK* - 20
1
(1 + nm*2 / 2) MCLK*1 + 20
ns
tLOW tHIGH tHD;STA tSU;STO tSU;STA tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT
ns ns ns ns ns ns ns ns ns ns
tLOW - 3 MCLK* - 20
1
0 MCLK*1 - 20
MB95100A Series
(Continued) Symbol tWAKEUP
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) I/O Timing Min Oscillation stabilization wait time + 2 MCLK*1 - 20 Max Unit Remarks
Parameter SDASCL (at wakeup function)
ns
*1 : Refer to " (2) Source Clock/Machine Clock" for MCLK. *2 : * * * * m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) . n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) . Actual timing of I2C is determined by m and n values set by the machine clock (MCLK) and ICCR [4 : 0]. Standard-mode : m and n can be set at the range : 0.9 MHz < MCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < MCLK 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < MCLK 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < MCLK 4 MHz (m, n) = (1, 98) : 0.9 MHz < MCLK 10 MHz
* Fast-mode : m and n can be set at the range : 3.3 MHz < MCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < MCLK 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < MCLK 8 MHz (m, n) = (6, 4) : 3.3 MHz < MCLK 10 MHz
50
MB95100A Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics (AVcc = Vcc = 1.8 V to 3.3 V [FLASH product], AVcc = Vcc = 1.8 V to 3.6 V [MASK product], AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Resolution Total error Linearity error Differential linear error Symbol Value Min - 3.0 - 2.5 - 1.9 AVss - 1.5 LSB AVss - 0.5 LSB AVR - 3.5 LSB AVR - 2.5 LSB Typ AVss + 0.5 LSB AVss + 1.5 LSB AVR - 1.5 LSB AVR - 0.5 LSB Max 10 + 3.0 + 2.5 + 1.9 AVss + 2.5 LSB AVss + 3.5 LSB AVR + 0.5 LSB AVR + 1.5 LSB Unit bit LSB LSB LSB FLASH product : 2.7 V AVcc 3.3 V MASK product : 2.7 V AVcc 3.6 V 1.8 V AVcc < 2.7 V FLASH product : 2.7 V AVcc 3.3 V MASK product : 2.7 V AVcc 3.6 V 1.8 V AVcc < 2.7 V FLASH product : 2.7 V AVcc 3.3 V MASK product : 2.7 V AVcc 3.6 V 1.8 V AVcc < 2.7 V FLASH product : 2.7 V AVcc 3.3 V MASK product : 2.7 V AVcc 3.6 V external impedance < at 1.8 k 1.8 V AVcc < 2.7 V external impedance < at 14.8 k Remarks
V
Zero transition voltage
VOT
V
Full-scale transition voltage
V
VFST
V
Compare time
0.6
16,500
s s
20
16,500
0.4 Sampling time
s
30 Analog input current Analog input voltage range Reference voltage Reference voltage supply current IAIN VAIN IR IRH -0.3 AVss AVss + 1.8
400
0.3 AVR AVcc 600 5
s A V V A A
AVR pin AVR pin, During A/D operation AVR pin, At stop mode
51
MB95100A Series
(2) Notes on Using A/D Converter * About the external impedance of analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model
R
Analog input pin
C
Comparator
During sampling : ON 2.7 V AVcc 3.6 V 1.8 V AVcc < 2.7 V Note : The values are reference values. R 1.7 k (Max) 84 k (Max) C 14.5 pF (Max) 25.2 pF (Max)
* To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between external impedance and minimum sampling time (External impedance = 0 k to 100 k)
AVCC 2.7 V
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15
(External impedance = 0 k to 20 k)
AVCC 2.7 V
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4
External impedance [k]
AVCC 1.8 V
20
25
30
35
40
External impedance [k]
Minimum sampling time [s]
Minimum sampling time [s]
* If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * About errors As |AVR - AVSS| becomes smaller, values of relative errors grow larger.
52
MB95100A Series
(3) Definition of A/D Converter Terms * Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") of a device and the full-scale transition point ("11 1111 1111" "11 1111 1110") compared with the actual conversion values obtained. * Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. * Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise.
Ideal I/O characteristics
VFST
Total error
3FFH 3FEH
3FFH 3FEH 1.5 LSB
Actual conversion characteristic {1 LSB x (N - 1) + 0.5 LSB}
Digital output
Digital output
3FDH
3FDH
004H 003H 002H 001H 0.5 LSB AVSS AVR VOT 1 LSB
004H 003H 002H 001H AVSS AVR VNT Actual conversion characteristic Ideal characteristics
Analog input 1 LSB = AVR - AVss 1024 (V)
Analog input
Total error of VNT - {1 LSB x (N - 1) + 0.5 LSB} = [LSB] digital output N 1 LSB
VNT : A voltage at which digital output transits from (N - 1) to N.
(Continued)
53
MB95100A Series
(Continued) Zero transition error
004H
Actual conversion characteristic
Full-scale transition error
Ideal characteristics
3FFH
Digital output
003H
Ideal characteristics
Digital output
Actual conversion characteristic
3FEH
VFST
002H
Actual conversion characteristic
3FDH
(measurement value)
001H
VOT (measurement value)
Actual conversion characteristic
3FCH
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error
3FFH 3FEH
Actual conversion characteristic
Differential linear error
Ideal characteristics
N+1 {1 LSB x N + VOT}
VFST
(measurement value)
Digital output
Digital output
3FDH
Actual conversion characteristic
V (N+1)T
N
VNT 004H 003H 002H 001H AVSS
Actual conversion characteristic Ideal characteristics
N-1
VNT
Actual conversion characteristic
N-2
VOT (measurement value)
Analog input
AVR
AVSS
Analog input
AVR
Linear error in = VNT - {1 LSB x N + VOT} 1 LSB digital output N
Differential linear error = in digital output N
V (N + 1) T - VNT 1 LSB
-1
VNT : A voltage at which digital output transits from (N - 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR - 1.5 LSB [V]
54
MB95100A Series
6. Flash Memory Program/Erase Characteristics
Parameter Sector erase time (4 KB sector) Sector erase time (16 KB sector) Byte programming time Erase/program cycle Power supply voltage at erase/ program Flash data retension time Value Min 10,000 2.7 20*3 Typ 0.2*1 0.5*1 32 Max 3*2 12*2 3600 3.3 Unit s s s cycle V year Average TA = +85 C Remarks Excludes 00H programming prior erasure. Excludes 00H programming prior erasure. Excludes system-level overhead.
*1 : TA = + 25 C, VCC = 3.0 V, 10000 cycles *2 : TA = + 85 C, VCC = 2.7 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) .
55
MB95100A Series
MASK OPTION
Part number No. Specifying procedure Clock mode select * Single-system clock mode * Dual-system clock mode Selection of oscillation stabilization wait time * Selectable the initial value of main clock oscillation stabilization wait time MB95107A MB95F108AS MB95F108AW MB95FV100A-101 Specify when Setting disabled Setting disabled Setting disabled ordering MASK Selectable Selectable 1 : (22-2) /FCH 2 : (212-2) /FCH 3 : (213-2) /FCH 4 : (214-2) /FCH Single-system clock mode Fixed to oscillation stabilization wait time of (214-2) /FCH Dual-system clock mode Fixed to oscillation stabilization wait time of (214-2) /FCH Changing by the switch on MCU board Fixed to oscillation stabilization wait time of (214-2) /FCH
1
2
ORDERING INFORMATION
Part number MB95107APFV MB95F108ASPFV MB95F108AWPFV MB95107APFM MB95F108ASPFM MB95F108AWPFM MB2146-301 (MB95FV100A-101PBT) Package 64-pin plastic LQFP (FPT-64P-M03) 64-pin plastic LQFP (FPT-64P-M09) Remarks
(
MCU board 224-pin plastic PFBGA (BGA-224P-M08)
)
56
MB95100A Series
PACKAGE DIMENSIONS
64-pin plastic LQFP (FPT-64P-M03)
12.000.20(.472.008)SQ
* 10.000.10(.394.004)SQ
48 33
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
49
32
Details of "A" part 0.08(.003) 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
64 17
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.25(.010)
LEAD No.
1
16
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
C
2003 FUJITSU LIMITED F64009S-c-5-8
Dimensions in mm (inches). Note: The values in parentheses are reference values. (Continued)
57
MB95100A Series
(Continued) 64-pin plastic LQFP (FPT-64P-M09)
14.000.20(.551.008)SQ
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
* 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
58
MB95100A Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0502 (c) 2005 FUJITSU LIMITED Printed in Japan

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